field-programmable gate array - определение. Что такое field-programmable gate array
Diclib.com
Словарь ChatGPT
Введите слово или словосочетание на любом языке 👆
Язык:

Перевод и анализ слов искусственным интеллектом ChatGPT

На этой странице Вы можете получить подробный анализ слова или словосочетания, произведенный с помощью лучшей на сегодняшний день технологии искусственного интеллекта:

  • как употребляется слово
  • частота употребления
  • используется оно чаще в устной или письменной речи
  • варианты перевода слова
  • примеры употребления (несколько фраз с переводом)
  • этимология

Что (кто) такое field-programmable gate array - определение

INTEGRATED CIRCUIT DESIGNED TO BE CONFIGURED BY A CUSTOMER OR A DESIGNER AFTER MANUFACTURING
Field programmable gate array; FPGA; FPGAs; Field Programmable Gate Array; Programmable gate array; Fpga; Field programmable logic array; Field-Programmable Gate Array; Programmable Gate Array; Field-programmable gate arrays; FPGA board
  • Stratix IV]] FPGA from [[Altera]]
  • D-type flip-flop]])
  • A Spartan FPGA from [[Xilinx]]
  • A [[Xilinx]] Zynq-7000 All Programmable System on a Chip
Найдено результатов: 5021
field-programmable gate array         
<hardware> (FPGA) A gate array where the logic network can be programmed into the device after its manufacture. An FPGA consists of an array of logic elements, either gates or lookup table RAMs, flip-flops and programmable interconnect wiring. Most FPGAs are reprogrammable, since their logic functions and interconnect are defined by RAM cells. The Xilinx LCA, Altera FLEX and AT&T ORCA devices are examples. Others can only be programmed once, by closing "antifuses". These retain their programming permanently. The Actel FPGAs are the leading example of such devices. Atmel FPGAs are currently (July 1997) the only ones in which part of the array can be reprogrammed while other parts are active. As of 1994, FPGAs have logic capacity up to 10K to 20K 2-input-NAND-equivalent gates, up to about 200 I/O pins and can run at clock rates of 50 MHz or more. FPGA designs must be prepared using CAD software tools, usually provided by the chip vendor, to do technology mapping, partitioning and placement, routing, and binary output. The resulting binary can be programmed into a ROM connected to the FPGA or downloaded to the FPGA from a connected computer. In addition to ordinary logic applications, FPGAs have enabled the development of logic emulators. There is also research on using FPGAs as computing devices, taking direct advantage of their reconfigurability into problem-specific hardware processors. Usenet newsgroup: news:comp.arch.fpga. (1997-07-11)
Field-programmable gate array         
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term field-programmable. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).
FPGA         
Field Programmable Gate Array (Reference: RL)
FPGA         
Generic Array Logic         
  • Lattice]] GAL16V8D-15LJ
TYPE OF DIGITAL CIRCUIT
Programmable electrically erasable logic; Gate Array Logic; Generic array logic
<hardware, integrated circuit> (GAL) A newer kind of Programmable Array Logic based on EEPROM storage cells, been pioneered by Lattice. GALs can be erased and reprogrammed and usually replace a whole set of different PALs (hence the name). (1995-12-09)
Generic array logic         
  • Lattice]] GAL16V8D-15LJ
TYPE OF DIGITAL CIRCUIT
Programmable electrically erasable logic; Gate Array Logic; Generic array logic
The Generic Array Logic (also known as GAL and sometimes as gate array logic) device was an innovation of the PAL and was invented by Lattice Semiconductor. The GAL was an improvement on the PAL because one device type was able to take the place of many PAL device types or could even have functionality not covered by the original range of PAL devices.
Field-programmable object array         
  • Simplified illustration of FPOA architecture. The area between the rectangles forms peripheral circuitry and the oval around the object interface it to the rest of FPOA.
CLASS OF PROGRAMMABLE LOGIC DEVICE DESIGNED TO BE MODIFIED OR PROGRAMMED AFTER MANUFACTURING
Fpoa; FPOA; Field programmable object array
A field-programmable object array (FPOA) is a class of programmable logic devices designed to be modified or programmed after manufacturing. They are designed to bridge the gap between ASIC and FPGA.
Programmable Array Logic         
  • AMD 22V10 in 24-pin DIP
  • counter]]
  • The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as ''product terms'', are ORed together to form a ''sum-of-products'' logic array.
  • AMD Palce 16V8H-25JC
TYPE OF PROGRAMMABLE LOGIC DEVICE
John Birkner; Programmable array logic
Programmable Array Logic (PAL) is a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in March 1978.
Gate array         
  • Uncommitted Logic Array}} 2C210E on a [[Timex Sinclair 1000]] motherboard
TYPE OF APPLICATION-SPECIFIC INTEGRATED CIRCUIT
Gate-array; Uncommitted logic array; Uncommitted Logic Array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g.
Programmable Array Logic         
  • AMD 22V10 in 24-pin DIP
  • counter]]
  • The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as ''product terms'', are ORed together to form a ''sum-of-products'' logic array.
  • AMD Palce 16V8H-25JC
TYPE OF PROGRAMMABLE LOGIC DEVICE
John Birkner; Programmable array logic
<hardware> (PAL) A family of fuse-programmable logic integrated circuits originally developed by MMI. Registered or combinatorial output functions are modelled in a sum of products form. Each output is a sum (logical or) of a fixed number of products (logical and) of the input signals. This structure is well suited for automatic generation of programming patterns by logic compilers. PAL devices are programmed by blowing the fuses permanently using overvoltage. Today, more complex devices based on the same original architecture are available (CPLD's for Complex PLD's) that incorporate the equivalent of several original PAL chips. PAL chips are, however, still popular due to their high speed. Generic Array Logic devices are reprogrammable and contain more logic gates. (1995-12-09)

Википедия

Field-programmable gate array

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term field-programmable. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools.

FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions, or act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurable computing as performed in computer software.

FPGAs have a remarkable role in embedded system development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture.